A54SX16A-PQG208A Datasheet, PDF (32/68 Pages) Actel Corporation – SX-A Automotive Family FPGAs

Table 1-14 • A54SX16A Timing Characteristics
(Worst-Case Automotive Conditions, V_CCA = 2.3 V, V_CCI = 3.0 V , T_J = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
Min
Max.
Units
d_TLH
Delta LOW to HIGH
d_THL
Delta HIGH to LOW
d_THLS
Delta HIGH to LOW—low slew
3.3 V PCI Output Module Timing⁴
0.064
0.029
0.108
ns/pF
ns/pF
ns/pF
t_DLH
Data-to-Pad LOW to HIGH
t_DHL
Data-to-Pad HIGH to LOW
t_ENZL
Enable-to-Pad, Z to L
t_ENZH
Enable-to-Pad, Z to H
t_ENLZ
Enable-to-Pad, L to Z
t_ENHZ
Enable-to-Pad, H to Z
d_TLH
Delta LOW to HIGH
d_THL
Delta HIGH to LOW
3.3 V LVTTL Output Module Timing³
3.8
3.8
2.8
2.8
4.8
4.8
0.050
0.019
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
t_DLH
Data-to-Pad LOW to HIGH
5.3
ns
t_DHL
Data-to-Pad HIGH to LOW
4.8
ns
t_DHLS
Data-to-Pad HIGH to LOW—low slew
17.3
ns
t_ENZL
Enable-to-Pad, Z to L
4.3
ns
t_ENZLS
Enable-to-Pad, Z to L—low slew
31.9
ns
t_ENZH
Enable-to-Pad, Z to H
5.5
ns
t_ENLZ
Enable-to-Pad, L to Z
5.5
ns
t_ENHZ
Enable-to-Pad, H to Z
4.8
ns
d_TLH
Delta LOW to HIGH
0.050
ns/pF
d_THL
Delta HIGH to LOW
0.019
ns/pF
d_THLS
Delta HIGH to LOW—low slew
0.092
ns/pF
Notes:
1. For dual-module macros, use t_PD + t_RD1 + t_PDn , t_RCO + t_RD1 + t_PDn or t_PD1 + t_RD1 + t_SUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
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