RT54SX32-1CQ256B Datasheet, PDF (31/46 Pages) Actel Corporation – SX Family FPGAs RadTolerant and HiRel

SX Family FPGAs RadTolerant and HiRel
Table 1-18 • RT54SX32 Timing Characteristics
(Worst-Case Military Conditions, V_CCR = 4.75 V, V_CCA, V_CCI = 3.0 V, T_J = 125°C)
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
I/O Module – TTL Output Timing*
t_DLH
Data-to-Pad LOW to HIGH
t_DHL
Data-to-Pad HIGH to LOW
t_ENZL
Enable-to-Pad, Z to LOW
t_ENZH
Enable-to-Pad, Z to HIGH
t_ENLZ
Enable-to-Pad, LOW to Z
t_ENHZ
Enable-to-Pad, HIGH to Z
d_TLH
Delta LOW to HIGH
d_THL
Delta HIGH to LOW
Dedicated (Hardwired) Array Clock Network
5.1
6.0
5.1
6.0
4.2
5.1
5.1
6.0
8.1
9.4
4.0
4.7
0.09
0.11
0.09
0.15
t_HCKH
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
3.6
t_HCKL
Input HIGH to LOW
(Pad to R-Cell Input)
3.5
4.0
t_HPWH
Minimum Pulse Width HIGH
t_HPWL
Minimum Pulse Width LOW
t_HCKSW
Maximum Skew
t_HP
Minimum Period
f_HMAX
Maximum Frequency
Routed Array Clock Networks
3.8
4.4
3.8
4.4
0.8
0.8
7.6
8.9
130
110
t_RCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
4.4
5.3
t_RCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
4.9
5.6
t_RCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
5.3
6.0
t_RCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
5.3
6.3
t_RCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
5.1
6.0
t_RCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
5.3
6.3
t_RPWH
Minimum Pulse Width HIGH
5.6
6.7
t_RPWL
Minimum Pulse Width LOW
5.6
6.7
Note: *Delays based on 35 pF loading, except t_ENZL and t_ENZH. For t_ENZL and t_ENZH the loading is 5 pF.
Units
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
v2.1
1-27