RTSX72SU-1CQ256B Datasheet, PDF (29/83 Pages) Actel Corporation – RTSX-SU RadTolerant FPGAs (UMC)

RTSX-SU RadTolerant FPGAs (UMC)
Timing Characteristics
Table 2-14 • RTSX32SU 5V CMOS I/O Module
Worst-Case Military Conditions V_CCA = 2.25V, V_CCI = 4.5V, T_J = 125°C, Radiation Level = 0 krad (Si)
‘–1’ Speed
‘Std.’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
5V CMOS Output Module Timing
t_INYH
t_INYL
t_DLH
t_DHL
t_DHLS
t_ENZL
t_DENZLS
t_ENZH
t_ENLZ
t_ENHZ
d_TLH2
d_THL2
d_THLS2
Notes:
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to Low
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to High
Enable-to-Pad, Low to Z
Enable-to-Pad, High to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low – low slew
0.7
1.1
3.4
3.6
8.7
2.3
8.8
3.6
4.5
3.4
0.036
0.029
0.049
0.9
1.3
4.0
4.2
10.3
2.8
10.4
4.2
5.3
4.0
0.046
0.038
0.064
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCI value into the following equation:
Slew Rate [V/ns] = (0.1*V_CCI - 0.9*V_CCI)/ (C_load * d_TLH|d_THL|d_THLS)
where C_load is the load capacitance driven by the I/O in pF;
d_TLH|d_THL|d_THLS is the worst case delta value from the datasheet in ns/pF.
Table 2-15 • RTSX72SU 5V CMOS I/O Module
Worst-Case Military Conditions V_CCA = 2.25V, V_CCI = 4.5V, T_J = 125°C, Radiation Level = 0 krad (Si)
‘–1’ Speed
‘Std.’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
5V CMOS Output Module Timing
t_INYH
t_INYL
t_DLH
t_DHL
t_DHLS
t_ENZL
t_DENZLS
t_ENZH
t_ENLZ
t_ENHZ
d_TLH2
d_THL2
d_THLS2
Notes:
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
Data-to-Pad Low to High
Data-to-Pad High to Low
Data-to-Pad High to Low – low slew
Enable-to-Pad, Z to Low
Enable-to-Pad, Z to Low – low slew
Enable-to-Pad, Z to High
Enable-to-Pad, Low to Z
Enable-to-Pad, High to Z
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low – low slew
0.7
0.0
3.6
3.8
9.2
2.3
8.8
3.8
4.5
3.6
0.036
0.029
0.049
0.9
0.0
4.2
4.5
10.8
2.8
10.4
4.5
5.3
4.2
0.046
0.038
0.064
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns/pF
ns/pF
ns/pF
1. Output delays based on 35 pF loading.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCI value into the following equation:
Slew Rate [V/ns] = (0.1*V_CCI - 0.9*V_CCI)/ (C_load * d_TLH|d_THL|d_THLS)
where C_load is the load capacitance driven by the I/O in pF;
d_TLH|d_THL|d_THLS is the worst case delta value from the datasheet in ns/pF.
v2.2
2-15