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A1010B-PLG68I Datasheet, PDF (28/98 Pages) Actel Corporation – Highly Predictable Performance with 100% Automatic Placement and Routing
A1240A Timing Characteristics (continued)
(Worst-Case Military Conditions, VCC = 4.5V, TJ = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
tINYL
Pad to Y Low
tINGH
G to Y High
tINGL
G to Y Low
Input Module Predicted Routing Delays1
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Global Clock Network
4.0
4.7
ns
3.6
4.3
ns
6.9
8.1
ns
6.6
7.7
ns
5.8
6.9
ns
6.7
7.8
ns
7.5
8.8
ns
8.2
9.7
ns
10.9
12.9
ns
tCKH
Input Low to High
FO = 32
FO = 256
13.3
16.3
15.7
19.2
ns
tCKL
Input High to Low
FO = 32
FO = 256
13.3
16.5
15.7
19.5
ns
tPWH
Minimum Pulse Width High
FO = 32
5.7
FO = 256
6.0
6.7
7.1
ns
tPWL
Minimum Pulse Width Low
FO = 32
5.7
FO = 256
6.0
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 32
0.6
FO = 256
3.1
0.6
3.1
ns
tSUEXT
Input Latch External Setup
FO = 32
0.0
FO = 256
0.0
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
8.6
FO = 256
13.8
8.6
13.8
ns
tP
Minimum Period
FO = 32
11.5
FO = 256
12.2
13.5
14.3
ns
fMAX
Maximum Frequency
FO = 32
87
FO = 256
82
74
70
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
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