EP201 Datasheet, PDF (2/2 Pages) Actel Corporation – EP201 PowerPC Bus Master

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EP201 PowerPC Bus Master
DESCRIPTIONS
OPTIONAL
FEATURES
The PowerPC bus master is a bus interface unit designed for the PowerPC host
bus. It allows the user to initiate data transfer directly on the PowerPC CPU bus
through a very simple user interface.
The PowerPC bus master arbitrates for the PowerPC address bus before starting
any transfers. It handles separate address and data bus tenure so that data bus is
arbitrated independently from the address bus. The bus master handles address
retry by the CPU or other sources on the CPU bus. Upon address retry, it automat-
ically re-starts the data transfer unless an error has occurred.
Single beat, burst data and extended MPC8260 data transfer are supported. Differ-
ent data size and transfer types are allowed and can be specified through an inter-
nal back-end bus. There are two user interface ports provided by the bus master. It
allows two different devices to access the PowerPC bus through a single bus mas-
ter. The bus master contains arbitration logic to arbitrate between the two request
ports.
The following table summarizes the optional features which can be provided with
the core as required by user application.
Options
Extended data transfer
Dual or single user interface
Address only transfer
Description
MPC8260 extended data transfer
Supports one, two or multiple user request
ports.
Execute address only transfer on the CPU bus
for data snooping.
Actel Device
Utilization
Data
Family
ProASICPlus
Axcelerator
RTSX-S
Device
(-speed grade)
APA150-STD
AX500-3
RT54SX32S-2
Utilization
Performance
SEQ COMB Total RAM
452 882
22%
40Mhz
408 290
9%
126Mhz
410 281
24%
61Mhz
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