APA1000-FFGG1152I Datasheet, PDF (167/174 Pages) Actel Corporation – ProASIC Flash Family FPGAs

ProASIC^PLUS Flash Family FPGAs
Previous version Changes in current version (v5.7)
v3.5
The ProASIC^PLUS and ProASIC^PLUS Military/Aerospace datasheets were combined. This
document now supports Commercial, Industrial, and Military Temperature devices.
Page
Table 1 was updated.
page i-i
The "Ordering Information" section was updated.
page i-ii
"Plastic Device Resources" table was updated.
page i-ii
The Long Term Jitter Peak-to-Peak Max. in the "PLL Electrical Specifications" table was updated. page 1-21
The "Calculating Typical Power Dissipation" section was updated.
page 1-30
"Performance Retention" section
page 1-33
Table 1-18
page 1-34
Table 1-20 was updated.
page 1-35
Table 1-21 was updated.
page 1-36
Table 1-22 was updated.
page 1-38
Table 1-46 was updated.
page 1-52
v3.4
The "Temperature Grade Offerings" table is new.
page i-iv
The "Speed Grade and Temperature Matrix" table is new.
page i-iv
The "ProASICPLUS Clock Management System" section was updated.
page 1-13
The "Lock Signal" section was updated.
page 1-16
The "PLL Electrical Specifications" table was updated.
page 1-21
The "User Security" section was updated.
page 1-22
The "Design Environment" section was updated.
page 1-27
Table 1-15 was updated.
page 1-29
The "Asynchronous FIFO Full and Empty Transitions" section was updated.
page 1-65
The "AVDD PLL Power Supply" section in the "Pin Description" section was updated.
page 1-73
v3.3
The "144-Pin TQFP" table on page 2-4 was updated. The following pins changed:
page 2-4
Pin 15 = GLMX1
Pin 16 = GL1
Pin 21 = GL2
Pin 88 = GL3
Pin93 = GL4
Pin 94 = GLMX2
v3.2
The "ProASICPLUS Clock Management System" section was updated.
page 1-13
Figure 1-14 was updated.
page 1-14
Table 1-7 is new.
page 1-15
Figure 1-20 was updated.
page 1-19
The "PLL Electrical Specifications" section was updated.
page 1-21
Figure 1-26 was updated.
page 1-42
In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW.
page 1-30
The "Programming, Storage, and Operating Limits" section was updated.
page 1-33
The "Recommended Design Practice for VPN/VPP" section was updated.
page 1-74
v3.1
The datasheet was updated to include references to guidelines concerning the use of certain
ProASIC^PLUS I/O standards.
v3.0
In Table 1-2 on page 1-8, the Memory Rows – Bottom coordinates were changed.
page 1-8
Figure 1-8 was updated.
page 1-8
The V_IL Minimum in the Table 1-22 was changed from 0.3 to –0.3.
page 1-38
In the "Output Buffer Delays" section, the OB25LPLL t_DHL Standard changed to 5.3.
page 1-44
In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7 page 1-51
and the –F maximum changed to 0.8.
v5.7
3-3