A1020B-PL84C Datasheet, PDF (16/24 Pages) Actel Corporation – ACT™ 1 Series FPGAs

ACT 1 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_INYH
Pad to Y High
t_INYL
Pad to Y Low
Input Module Predicted Routing Delays¹
3.1
3.5
4.0
4.7
6.8 ns
3.1
3.5
4.0
4.7
6.8 ns
t_IRD1
FO=1 Routing Delay
t_IRD2
FO=2 Routing Delay
t_IRD3
FO=3 Routing Delay
t_IRD4
FO=4 Routing Delay
t_IRD8
FO=8 Routing Delay
Global Clock Network
0.9
1.1
1.2
1.4
2.0 ns
1.4
1.7
1.9
2.2
3.2 ns
2.1
2.5
2.8
3.3
4.8 ns
3.1
3.6
4.1
4.8
7.0 ns
6.6
7.7
8.7
10.2
14.8 ns
t_CKH
Input Low to High
FO = 16
4.9
5.6
6.4
7.5
6.7
FO = 128
5.6
6.4
7.3
8.6
7.9 ns
t_CKL
Input High to Low
FO = 16
6.4
7.4
8.4
9.9
8.8
FO = 128
7.0
8.1
9.2
10.8
10.0 ns
t_PWH
Minimum Pulse Width FO = 16 6.5
7.5
8.5
10.0
8.9
High
FO = 128 6.8
8.0
9.0
10.5
9.8
ns
t_PWL
Minimum Pulse Width FO = 16 6.5
7.5
8.5
10.0
8.9
Low
FO = 128 6.8
8.0
9.0
10.5
9.8
ns
t_CKSW
Maximum Skew
FO = 16
1.2
1.3
1.5
1.8
1.5
FO = 128
1.8
2.1
2.4
2.8
2.4 ns
t_P
Minimum Period
FO = 16 13.2
15.4
17.6
20.9
18.2
FO = 128 14.2
16.7
18.9
22.3
20
ns
f_MAX
Maximum Frequency
FO = 16
75
65
57
48
55
FO = 128
70
60
53
45
50 MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior
to shipment.
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