A1010B-PQ100C Datasheet, PDF (16/98 Pages) Actel Corporation – HiRel FPGAs

3200DX Timing Model (SRAM Functions)*
Input Delays
I/O Module
t_INPY = 1.9 ns _{tIRD1 = 2.2 ns}
DQ
G
t_INSU = 0.7 ns
t_INH = 0.0 ns
t_INGO = 4.0 ns
ARRAY
CLOCKS
F_MAX = 140 MHz
WD [7:0]
WRAD [5:0]
BLKEN
WEN
WCLK
t_ADSU = 2.1 ns
t_ADH = 0.0 ns
t_WENSU = 3.5 ns
t_BENS = 3.6 ns
RD [7:0]
RDAD [5:0]
REN
RCLK
t_ADSU = 2.1 ns
t_ADH = 0.0 ns
t_RENSU = 0.8 ns
t_RCO = 4.4 ns
Predicted
Routing
Delays
t_RD1 = 1.3 ns
*Values shown for A32100DX–1 at worst-case military conditions.
I/O Module
t_DLH = 6.3 ns
DQ
G
t_GHL = 12.4 ns
t_LSU = 0.4 ns
t_LH = 0.0 ns
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