A1010B-PL68C Datasheet, PDF (14/24 Pages) Actel Corporation – ACT™ 1 Series FPGAs

Sequential Timing Characteristics
Flip-Flops and Latches
D
PRE
Q
E
CLK
CLR
(Positive edge triggered)
D¹
CLK
E
Q
PRE, CLR
t_SUD
t_HD
t_WCLKA
t_SUENA
t_CO
t_A
t_RS
t_WASYN
Note: D represents all data functions involving A, B, S for multiplexed flip-flops.
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