A1020B-PLG84C Datasheet, PDF (13/24 Pages) Actel Corporation – 5V and 3.3V Families fully compatible with JEDEC specifications

Parameter Measurement
Output Buffer Delays
ACT^™ 1 Series FPGAs
E
D
TRIBUFF
PAD To AC test loads (shown below)
In
PAD
V_OL
V_CC
50% 50%
V_OH
1.5 V
GND
1.5 V
t_DLH
t_DHL
E
PAD
V_CC
50% 50%
V_CC
1.5 V
V_OL
GND
10%
t_ENZL
t_ENLZ
E
PAD
GND
V_CC
50% 50%
V_OH
1.5 V
GND
90%
t_ENZH
t_ENHZ
AC Test Loads
Load 1
(Used to measure propagation delay)
To the output under test
35 pF
Load 2
(Used to measure rising/falling edges)
V_CC
GND
To the output under test
R to V_CC for t_PLZ/t_PZL
R to GND for t_PHZ/t_PZH
R = 1 kΩ
35 pF
Input Buffer Delays
PAD
INBUF
Y
PAD
Y
GND
3V
1.5 V 1.5 V
V_CC
50%
0V
50%
t_INYH
t_INYL
Module Delays
S
AY
B
S, A or B
Out
GND
Out
V_CC
50% 50%
V_CC
50%
GND
50%
t_PLH
50%
t_PHL
t_PHL
GND
t_PLH
V_CC
50%
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