MC-ACT-VME32-NET Datasheet, PDF (1/5 Pages) Actel Corporation – Flexible slave VME controller Full interrupt controller (ROAK)

AvnetCore: Datasheet
VME_ADDR[31:1]
VME_AM[5:0]
VME_DATA_IN[31:0]
VME_DATA_OUT[31:0]
VME_EXT_DRV_N
VME_EXT_DDIR
VME_INT_DRV_N
VME_DTACK_N
VME_AS_N
VME_DS0_N
VME_DS1_N
VME_LWORD_N
VME_WRITE_N
VME_BERR_N
VME_IACK_N
VME_IACKOUT_N
VME_IACKIN_N
VME_IRQ_N[6:0]
CLK
RESET_N
MC-ACT-VME32
USER_ADDR[31:1]
USER_AM[5:0]
USER_RW_N
USER_WR_DATA[31:0]
USER_BE1
USER_BE2
USER_RD_DATA[31:0]
USER_ACC_REQ
USER_ACC_RDY
USER_IREQ
USER_ILEV[2:0]
USER_IVEC[31:0]
USER_IACK
INT_USER_AM[5:0]
INT_USER_ADDR[31:1]
USER_ACC
MC-ACT-VME32 Pinout
The MC-ACT-VME32 core is used as interface for the VME standard bus. One side
contains all VME bus signals and the other side all the user signals. With the defined
address and address modifier, the user allows any masters on the VME bus to access
the IO, peripherals or memory placed on the user side.
The user has to describe two blocks which are connected to the “address
decoding” and to the “user side”. The “address decoding” is used to detect the access
and to allow the transfer on the corresponding board. It allows the user to build its own
address decoding without changing the code of the MC-ACT-VME32.
The MC-ACT-VME32 core provides a full interrupt controller based on seven
interrupt lines connected to the bus. The system release the interrupt on the
acknowledge (ROAK). The acknowledge is done on all boards connected on the bus
through a daisy-chain.
A complete VHDL test bench verifies every functions and addressing mode and
interrupts. These test benches are built as a self testing regression-test suite.
VME32
Intended Use:
— Medical systems
— Industrial controls: robotic, factory automation
Features:
— Flexible slave VME controller
— Full interrupt controller (ROAK)
— Control signals for external drivers and drivers on chip
— Synchronous user side interface for registers, peripherals and
memories
— User definable waitstates
— Synchronous, reliable design
— Expandable to full set of VME features
— Silicon proven design
Targeted Devices:
— SX-A Family
— Axcelerator^® Family
— ProASIC^PLUS® Family
Core Deliverables:
— Netlist Version
> Netlist compatible with the Actel Designer place and route tool
— RTL Version
> VHDL Source Code
> Test Bench
— All
> User Guide
Synthesis and Simulation Support:
— Synthesis: Synplicity^®
— Simulation: ModelSim^®
— Other tools supported upon request
Verification:
— Test Bench