MC-ACT-UL3LINK-NET Datasheet, PDF (1/5 Pages) Actel Corporation – Function compatible with ATM Forum Asynchronous/synchronous FIFO using RAM

AvnetCore: Datasheet
Version 1.0, July 2006
UTOPIA Level 3 Link
top_master.vhd
top_egr_master.vhd
wr_enb
wr_data
wr_flag
wr_clk
fifo_16.vhd/fifo_8.vhd
rd_enb
rd_data
rd_flag
egr_utopia_master.vhd
reset_n
top_ing_master.vhd
rd_enb
rd_data
rd_flag
rd_clk
fifo_16.vhd/fifo_8.vhd
wr_enb
wr_data
wr_flag
ing_utopia_master.vhd
increment
txclk
tx_data
txenb_n
txclav
tx_soc
txprty
tx_addr
rxclk
rxdata
rxenb_n
rx_clav
rx_prty
rx_soc
rx_addr
Block Diagram
Intended Use:
— Cell Processors
— Switch Fabrics
— Networking
— Telecommunications
Features:
— Function compatible with ATM Forum
— Asynchronous/synchronous FIFO using RAM
— Up to 256 phys supported
— 8/16/32 bit interfaces supported
— Simple system side FIFO interface
— Flow control and polling integrated
Targeted Devices:
— Axcelerator Family
Core Deliverables:
— Netlist Version
> Netlist compatible with the Actel Designer place and route tool
> Compiled RTL simulation model, compliant with the Actel
Libero^® environment
— RTL Version
> VHDL Source Code
— All
> User Guide
> Test Bench
UTOPIA (Universal Test and Operations PHY Interface for ATM) level 3 defines the
interface between the ATM or LINK layer and a Physical Layer (PHY) device. The
UTOPIA level 3 standard defines a full duplex interface with a Master/Slave format. The
Slave or LINK layer device responds to the requests from the PHY or Master device.
The Master performs PHY arbitration and initiates data transfers to and from the Slave.
The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in width, at up to
104 MHz, supporting an OC48 channel at 2.5 Gbps.
Synthesis and Simulation Support:
— Synthesis: Synplicity^®
— Simulation: ModelSim^®
— Other tools supported upon request
Verification:
— Test Bench
— Test Vectors