MC-ACT-UL2PHY Datasheet, PDF (1/4 Pages) Actel Corporation – ATM cell processors ATM switch fabrics

AvnetCore: Datasheet
Version 1.0, July 2006
UTOPIA Level 2 PHY
Transmit Interface
Receive Interface
User Control
MC-ACT-UL2PHY
ING_CLK
ING_ADR[4:0]
ING_CLAV
ING_ENB_N
ING_DATA[15:0]
ING_PRTY
ING_SOC
EGR_CLK
EGR_ADR[4:0]
EGR_CLAV
EGR_ENB_N
EGR_DATA[15:0]
EGR_PRTY
EGR_SOC
WR_CLK
WR_DATA[495:0]
WR_ENB[30:0]
INCREMENT[30:0]
A_FULL[30:0]
RD_CLK
RD_DATA[495:0]
RD_ENB[30:0]
DECREMENT[30:0]
FLAG[30:0]
EGR_PERR
RESET_N
Write Interface
Features:
— Supports Actel Axcelerator devicesI/O Peripherals
— Compliant with ATM Forum af-phy-0017.000 and
af-phy-0039.000
— Supports up to 31 PHYs
— Special single PHY mode for smaller footprint
— Automatic PHY polling and selection
— Supports both 8-bit and 16-bit interfaces
— Supports 52-byte and 54-byte cell lengths
— Sync or Asynch FIFOs using RAM blocks
Read Interface
Applications:
— ATM cell processors
— ATM switch fabrics
CompanionCore Facts
MC-ACT-UL2PHY Logic Symbol
UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 2 defines the
interface between the ATM or LINK layer and a Physical Layer (PHY) device. The
UTOPIA Level 2 standard defines a full duplex interface with a Master/Slave format.
The Slave or LINK layer device responds to the requests from the PHY or Master
device. The Master performs PHY arbitration and initiates data transfers to and from
the Slave. The ATM forum has defined the UTOPIA Level 2 as either 8 or 16 bits in
width, at up to 50 MHz, supporting an OC12 channel at 622Mbps.
Core Metrics
See Table 1
Provided with Core
Documentation
Design File Formats
Constraint Files
Verification Method
User Guide, Data Sheet
VHDL RTL, targeted netlist
None
HDL Testbench
Design Tool Requirements
Simulation Tool
Synthesis Tool
Place & Route Tool
ModelSim^® Actel 5.8b
Synplify^® for Actel 7.5.1a
Designer 6.0
Support
Core support provided by Avnet Memec;
Additional customization provided by Avnet Memec.