MC-ACT-UL2LINK-NET Datasheet, PDF (1/7 Pages) Actel Corporation – Function compatible with ATM Forum af-phy-0017.000 & af-phy-0039.000

AvnetCore: Datasheet
Version 1.0, July 2006
UTOPIA Level 2 Link
Intended Use:
— ATM Cell Processors
— ATM Switch Fabrics
wr_data
wr_enb
wr_clk
a_full
increment
rd_data
rd_enb
rd_clk
flag
decrement
TX FIFO
ing_perr
rd_data
rd_enb
decrement
empty
flag
Features:
— Function compatible with ATM Forum af-phy-0017.000 &
af-phy-0039.000
egr_data
— Asynchronous/synchronous FIFO using RAM
egr_addr
TX
Master
egr_soc
egr_enb_n
egr_clav
egr_prty
— Up to 31 PHYs supported
— 8/16 bit interfaces supported
egr_clk
— 52/54 byte cells supported
— Simple system side FIFO interface
— Simple system side FIFO interface
tex
RXt FIFO
wr_data
wr_enb
soc
increment
a_full
ing_data
ing_addr
Targeted Devices:
RX
Master
ing_soc
ing_enb_n
ing_clav
— Axcelerator Family
ing_prty
ing_clk
Core Deliverables:
— Netlist Version
> Netlist compatible with the Actel Designer place and route tool
> Compiled RTL simulation model, compliant with the Actel
Libero^® environment
— RTL Version
> VHDL Source Code
— All
Block Diagram
> User Guide
> Test Bench
UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 2 defines the
interface between the ATM or LINK layer and a Physical Layer (PHY) device. The
UTOPIA level 2 standard defines a full duplex interface with a Master/Slave format. The
Slave or LINK layer device responds to the requests from the PHY or Master device.
The Master performs PHY arbitration and initiates data transfers to and from the Slave.
The ATM forum has defined the UTOPIA Level 2 as either 8 or 16 bits in width, at up to
50MHz, supporting an OC12 channel at 622Mbps.
Synthesis and Simulation Support:
— Synthesis: Synplicity
— Simulation: ModelSim
— Other tools supported upon request
Verification:
— Test Bench
— Test Vectors