MC-ACT-UARTM-NET Datasheet, PDF (1/9 Pages) Actel Corporation – Multi-Channel UART Controller

AvnetCore: Datasheet
Version 1.0, July 2006
Multi-Channel UART Controller
CLK
RESET_N
Reset
Character
Timeout
A[m:0]
ADS_N
D[7:0]
CS_N
RD_N
WR_N
INTR
earlyRst
rst
FIFO(s)
UARTM
Parallel
to
Serial
UART Wrapper
UART Core
UART_RECV
Host_registers
UART_INTR
Serial
to
Parallel
UART_XMIT
UART_BAUD
SIN
CTS_N
DSR_N
DCD_N
RI_N
RTS_N
DTR_N
OUT1_N
OUT2_N
SOUT
Block Diagram
TThe Multichannel UART (Universal Asynchronous Receiver/Transmitter) is a FPGA
core that implements up to 16 UARTs in a single Actel device. These UARTs are com-
pletely independent in functionality, but share common logic to reduce its overall size
as compared to individual instantiations. Each UART channel is similar to the industry
standard 16550 device and is an upward solution to standard UARTs by providing
FIFOs in both the transmit and the receive paths.
Intended Use:
—
Features:
— Function similar to industry standard 16550
— Configurable number of channels of 4, 8 or 16
— Configurable FIFO depths
— Channel baud rates to 115 K Baud
— Inserts or deletes standard asynchronous communication bits
(start, stop, and parity) to or from the serial data
— Line break and detection
Targeted Devices:
— ProASIC^®3
— ProASIC^PLUS® Family
Core Deliverables:
— Netlist Version
> Netlist compatible with the Actel Designer place and route tool
— RTL Version
> VHDL Source Code
> Verilog Test Bench
— All
> User Guide
Synthesis and Simulation Support:
— Synthesis: Synplicity^®
— Simulation: ModelSim^®
— Other tools supported upon request
Verification:
— Test Bench
— Test Cases