MC-ACT-SDRAMDDR-NET Datasheet, PDF (1/5 Pages) Actel Corporation – Double Data Rate SDRAM Controller

AvnetCore: Datasheet
Version 1.0, July 2006
Double Data Rate
SDRAM Controller
Intended Use:
— Supports All Standard DDR SDRAM Memory Types
— High-Speed Networking
— Embedded Computing
— Digital Video
reset
sys_clk
ddr_clk_fb
smp_delay
fpga_clk
sys_cmd
sys_cmd_ack
read_en
ctlr_ready
sys_data_o
sys_data_valid
sys_data_i
sys_data_m
sys_addr
clk_module
ddr_clk
clkx2
smp_clk
fpga_clk
Control and Status
controller
fpga_clk
ddr_interface
ddr_addr
ddr_dm
ddr_bank
ddr_ras
ddr_cas
ddr_we
ddr_dqs
ddr_cs
ddr_cke
ddr_dq
DDR
SDRAM
Features:
— DDR SDRAM dynamic burst length support for burst lengths of
2, 4, or 8 per access
— Supports DRAM data path widths of 16, 32, 64, and 72 bits
— Supports multiple bank interleaving with read and write
commands, and all read and write commands are issued at the
earliest possible time with maximum efficiency
— CAS latency 2.0 support
— Support for the following commands: NOP, LOAD_MODE,
READ, READ w/ AUTO_PRECHARGE, WRITE, WRITE w/
AUTO_PRECHARGE, and AUTO_REFRESH
— Data mask support for write operations
— Support for 4 internal banks
— Controller provides automatic management of all four SDRAM
memory banks simultaneously
Targeted Devices:
— Axcelerator^® Family
— ProASIC^®3 Family
Block Diagram
This core conforms to the appropriate standard(s). In general, standards do not
define the internal user interface, only the external interfaces and protocols. Therefore,
Avnet Memec has created a simple FIFO interface to this core for easy user
connectivity. Please consult the appropriate standards document for all external
signaling. The Double Data Rate (DDR) Synchronous Dynamic Random Access
Memory (SDRAM) controller pro-vides the user with a simplified interface to industry
standard memory devices. The controller has been targeted to the Actel Axcelerator^®
and ProASIC^®3 families of platform FPGAs and can be reconfigured to provide a
solution customized to the user’s needs based on system and memory-specific require-
ments. The DDR SDRAM controller offers full support for SDRAM bank and row
management, supports four bank interleaving between commands, and executes all
commands with maximum efficiency. The extensive feature list makes this an extremely
flexible and efficient core to use.
Core Deliverables:
— Netlist Version
> Netlist compatible with the Actel Designer place and route tool
— RTL Version
> VHDL Source Code
> Test Bench
— All
> User Guide
Synthesis and Simulation Support:
— Synthesis: Synplicity^®
— Simulation: ModelSim^®
— Other tools supported upon request
Verification:
— Test Bench
— Test Vectors