MC-ACT-HDLC-NET Datasheet, PDF (1/5 Pages) Actel Corporation – UTOPIA Level 3 PHY

AvnetCore: Datasheet
Version 1.0, July 2006
UTOPIA Level 3 PHY
top_slave
rd_data
rd_enb
rd_clk
rd_flag
top_egr_slave
fifo_16 / fifo_8
reset_n
top_ing_slave
wr_data
wr_flag
wr_enb
wr_clk
fifo_16 / fifo_8
wr_data
wr_enb
a_full
tx_utopia3_slave
TxClk
TxData
TxEnb_n
TxClav
TxSoc
TxPrty
TxAddr
rd_data
rd_enb
rd_flag
rx_utopia3_slave
RxClk
RxData
RxEnb_n
RxClav
RxPrty
RxSoc
RxAddr
Block Diagram
UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 3 defines the
interface between the ATM or LINK layer and a Physical Layer (PHY) device. The
UTOPIA Level 3 standard defines a full duplex interface with a Master/Slave format.
The Slave or LINK layer device responds to the requests from the PHY or Master
device. The Master performs PHY arbitration and initiates data transfers to and from
the Slave. The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in
width, at up to 104 MHz, supporting an OC48 channel at 2.5 Gbps.
Intended Use:
— ATM Cell Processors
— PHY Processors
— ATM Bridges & Gaskets
— DSL ASSP interfaces
— UNI/MAC
— Microprocessor interfaces
Features:
— Function compatible with ATM Forum af-phy-0136.000
— Asynchronous/synchronous FIFO using RAM
— Up to 256 PHY ports supported
— 8/16/32 bit interfaces supported
— Direct and polled status
— Simple system side FIFO interface
— Flow control and polling integrated
Targeted Devices:
— Axcelerator^® Family
— ProASIC^®3 Family
— ProASIC^PLUS® Family
Core Deliverables:
— Netlist Version
> Compiled RTL simulation model, compliant with the Actel
Libero^® environment
> Netlist compatible with the Actel Designer place and route tool
— RTL Version
> VHDL Source Code
— All
> User Guide
> Test Bench
Synthesis and Simulation Support:
— Synthesis: Synplicity^®
— Simulation: ModelSim^®
— Other tools supported upon request
Verification:
— Test Bench
— Test Vectors