G704-E1 Datasheet, PDF (1/5 Pages) Actel Corporation – ISDN Terminal Equipment E2 Interface (multi G704 on chip) E1-ATM Interface

AvnetCore: Datasheet
Version 1.0, July 2006
G704-E1 Framer
reset_n
AHB Master Bus
AHB Slave Bus
int_rx_frame
int_tx_frame
int_bus_error
int_mac_paused
int_phy_status_changed
load_ebl
sda_in
MC-ACT--ETHCTRL
TX
FIFO
MAC
RX
FIFO
Serial
Management
Interface
Config/
Control
tx_en
tx_er
txd
col
crs
tx_clk
rx_en
rxd
rx_clk
rx_dv
rx_er
mdc
md_drv_n
md_dout
md_din
rx_ext_addr_check_match
dest_addr_avbl
src_addr_avbl
len_type_avbl
rx_shift_reg
Block Diagram
The MC-ACT-G704E1 Framer core is designed to handle synchronous frame
structures (Recommendation G.704) running on an E1 carrier. Transmitter and receiver
part are two completely independent blocks both capable of handling basic and multi
frames. Both perform functions such as overhead bit insertion / detection, CRC4
computation and check. A very flexible synchronization unit (Recommendation G.706)
synchronizes automatically or by means of an external frame sync signal. The frame
builder unit can be configured which of the overhead bits are to be inserted or not.
Avnet Memec cores are designed with the philosophy that no global elements
should be embedded within the core itself. Global elements include any of the following
components: STARTUP, STARTBUF, BSCAN, READBACK, Global Buffers, Fast Output
Primitives, IOB Elements, Clock Delay Components, and any of the Oscillator Macros.
Avnet Memec cores contain resources present in only the sequential and combinatorial
array. This is done to allow flexibility in using the cores with other logic. For instance, if
a global clock buffer is embedded within the core, but some external logic also requires
that same clock, then an additional global buffer would have to be used.
In any instance, where one of our cores generates a clock, that signal is brought
out of the core, run through a global buffer, and then brought back into the core. This
philosophy allows external logic to use that clock without using another global buffer.
A result of this philosophy is that the cores are not self-contained. External logic
must be connected to the core in order to complete it.
Intended Use:
— ISDN Terminal Equipment
— E2 Interface (multi G704 on chip)
— E1-ATM Interface
Features:
— G704 framing de-framing on E1 carriers
— Basic & multi frame alignment
— Alarm bit processing
— Customizable error counters
— Selectable conditions for loss of sync
— CRC4 error checking and monitoring
— Fully synchronous
Targeted Devices:
— SX-A Family
— Axcelerator^® Family
— ProASIC^PLUS® Family
Core Deliverables:
— Netlist Version
> Netlist compatible with the Actel Designer place and route tool
— RTL Version
> VHDL Source Code
> Test Bench
— All
> User Guide
Synthesis and Simulation Support:
— Synthesis: Synplicity^®
— Simulation: ModelSim^®
— Other tools supported upon request
Verification:
— Test Bench