EP300 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – EP300 PowerPC Bus Arbiter

Eureka Technology
FEATURES
Product Summary
EP300 PowerPC Bus Arbiter
• Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740,
750 and 8260.
• Supports up to eight PowerPC bus masters with unlimited slave device support.
• Supports two outstanding bus accesses.
• Supports address only transfer and address bus retry.
• Independent address bus and data bus tenure with separate bus grant and data
bus grant.
•Option for fixed priority assignment or rotating priority scheme.
• Designed for ASIC or programmable logic device implementations in various
system environments.
• Fully static design with edge triggered flip-flops.
• Optimized for Actel SX-A, RTSX-S, AX, and APA product families.
DESCRIPTIONS
The EP300 PowerPC bus arbiter provides all the necessary functions to arbitrate
multiple bus masters directly connected to the PowerPC host bus. The arbiter sup-
ports separate address and data bus tenure to realize the high performance allowed
by the PowerPC bus architecture. Separate address bus grant and data bus grant
signals are provided for each master device on the bus. The arbiter uses sophisti-
cated built-in state machines to coordinate the address bus tenure and the data bus
tenure. At any given cycle, up to two simultaneous bus accesses are allowed.
Bus request
One from each device
Previous
master
data bus
grant
Address bus
Priority
TS# ABB# DBB# TT
PowerPC Bus
Data bus grant
One to each device
Bus grant
One to each device
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