EP100 Datasheet, PDF (1/2 Pages) Actel Corporation – EP100 PowerPC Bus Slave

Eureka Technology
FEATURES
Product Summary
EP100 PowerPC Bus Slave
• Fully supports PowerPC™ 60x bus protocol including PowerPC 603, 604, 740,
750 and MPC8260.
• Provide PowerPC bus device access to memory and devices on user interface.
• Direct support for standard asynchronous SRAM and synchronous BURST
SRAM.
• Burst access support using conventional asynchronous SRAM.
• Additional back-end interface bus for on-chip and off-chip logic and register
access.
• Back-end interface supports user device with various wait states.
• Burst access support including MPC8260 extended transfer size.
• Write buffer supports write posting for the back-end bus interface.
• Handles separate address bus and data bus tenure.
• Supports PowerPC address pipeline for improve performance.
• Supports address bus retry generated by other external device.
• Qualified address data bus grant through the use of bus busy signals.
• Designed for ASIC and programmable logic device implementations in various
system environments.
• Fully static design with edge triggered flip-flops.
• Optimized for Actel SX-A, RTSX-S, AX, and APA product families.
PowerPC Host Bus
User
Logic
EP100
PowerPC Bus
Slave
A14-A0
OE#
WE#
CS#
D0-63
D7-D0
A14-A0
OE
WE
CS
SRAM and Burst SRAM
© 2003 by Eureka Technology Inc.
4962 El Camino Real,
Los Altos, CA 94022, USA
Page 1
Tel: [phone]
Fax: [phone]
http://www.eurekatech.com