CORESDLC-XX Datasheet, PDF (1/21 Pages) Actel Corporation – CoreSDLC

CoreSDLC
Product Summary
Intended Use
• ISDN D-Channel
• X.25 Networks
• Frame Relay Networks
• Custom Serial Interfaces
Key Features
• Based on Intel's 80C152 Global Serial Channel
Working in SDLC Mode
• Single and Double-Byte Address Recognition
• Address Filtering Enables Multicast and Broadcast
Addresses
• 16-bit (CRC-16) and 32-bit (CRC-32) Frame Check
Sequence
• NRZ and NRZI Data Encoding
• Automatic Bit Stuffing/Stripping
• 3-Byte Deep Internal Receive and Transmit FIFOs
• Full or Half-Duplex Operation
• Variable Baud Rate
• External or Internal Transmit and Receive Clocks
• Optional Preamble Generation
• Programmable Interframe Space
• Raw Transmit and Receive Testing Modes
• All Major Actel Device Families Supported
Supported Families
• Fusion
• ProASIC3/E
• ProASIC^PLUS
• Axcelerator
• SX-A
• RTSX-S
Core Deliverables
• Evaluation Version
– Compiled RTL Simulation Model Fully
Supported in Actel Libero^® Integrated Design
Environment (IDE)
• Netlist Version
– Structural Verilog and VHDL Netlists (with and
without I/O pads) Compatible with Actel's
Designer Software Place-and-Route Tool
– Compiled RTL Simulation Model Fully
Supported in Actel Libero IDE
• RTL Version
– Verilog and VHDL Core Source Code
– Core Synthesis Scripts
• Testbench (Verilog and VHDL)
Synthesis and Simulation Support
• Synthesis: Synplicity^®, Synopsys^® (Design Compiler^®
/ FPGA Compiler^TM / FPGA Express^TM), Exemplar^TM
• Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Core Verification
• Comprehensive VHDL and Verilog Testbenches
• User can Modify Testbench Using Existing Format
to Add Custom Tests
Contents
General Description ................................................... 1
CoreSDLC Device Requirements ................................ 3
CoreSDLC Verification ................................................ 3
I/O Signal Descriptions ............................................... 3
SDLC Protocol Overview ............................................ 4
Data Encoding ............................................................ 7
Bit Stuffing ................................................................. 7
Special Function Registers ......................................... 8
Modes of Operation ................................................ 15
General Description of the Transmitter .................. 16
General Description of the Receiver ....................... 17
Ordering Information .............................................. 20
List of Changes ......................................................... 21
Datasheet Categories ............................................... 21
December 2005
v4.0
1
© 2005 Actel Corporation