COREAPB3 Datasheet, PDF (1/5 Pages) Actel Corporation – CoreAPB3

CoreAPB3
Product Summary
Intended Use
• Intended for Use in Processor-Based Systems to
Implement the AMBA APB Bus Fabric
• Allows Connection of either AMBA, APB2, or APB3
Peripherals to an APB3 Master
• Configured for Easy and Automatic System Design
with CoreConsole
• To Be Used Only with APB Masters that Do Not
Have Built-In APB Address Decoding
Key Features
• Up to 16 Slave Devices (APB2 or APB3) Supported
• Automatic Connection to AHB Bridge
(CoreAHBtoAPB3) and APB Slaves, as well as APB3
Slaves
• Provides Configurable Address Decoding for APB
Slots
Benefits
• Allows Easy Connection of APB Devices to a
CoreMP7 or Cortex™-M1 Subsystem
• Auto Stitch in CoreConsole for Rapid Development
• Compatible with AMBA, CoreMP7, and Cortex-M1
Supported Device Families
• Fusion
• IGLOO™
• IGLOOe
• ProASIC^®3L
• ProASIC3
• ProASIC3E
Synthesis and Simulation Support
• Supported in the Actel Libero^® Integrated Design
Environment (IDE)
Verification and Compliance
• Compliant with AMBA
Contents
Contents ..................................................................... 1
General Description ................................................... 1
Pinout ......................................................................... 2
Connecting CoreAPB3 in CoreConsole ..................... 3
Utilization ................................................................... 3
Ordering Information ................................................ 3
List of Changes ........................................................... 4
Datasheet Categories ................................................. 4
General Description
Along with CoreAHBtoAPB3, the CoreAPB3 bus
component provides an AMBA APB fabric that supports
up to 16 APB slaves. CoreAHBtoAPB3 provides APB
address decoding in the form of select signals. CoreAPB3
is concerned with multiplexing the read data busses,
PREADY signals, and PSLVERR signals to send to
CoreAHBtoAPB3. Figure 1 gives an illustration of
CoreAPB3.
There is one APB master, which sends out a PSEL signal to
CoreAPB3. This is used by CoreAPB3, along with appropriate
bits from the PADDR bus, to decode the appropriate PSELS
signal. This address decoding is dependent on the RangeSize
hardware parameter/generic. All 16 APB slots are always
of equal size. However, this size may be configured as
any value from 256 locations to 1 M locations by setting
RangeSize appropriately (via CoreConsole).
From Bridge
PSTB
PA[31:0]
PWDATA[31:0]
PWRITE
PSEL
To Bridge _PRDATA[31:0]
Figure 1 • CoreAPB3
To APB Slaves
PRDATA[31:0]
PRDATA[31:0]
PRDATA[31:0]
From Slave 1
From Slave 2
From Slave N
January 2008
v2.1
1
© 2008 Actel Corporation