COREAHB Datasheet, PDF (1/7 Pages) Actel Corporation – CoreAHB

CoreAHB
Product Summary
Contents
Intended Use
• CoreAHB Provides an AHB Bus Fabric and Is
Intended for Use in an AMBA Subsystem where
Multiple AHB Masters are Present
Key Features
• Supplied in SysBASIC Core Bundle
• Implements a Multi-Master AMBA AHB Bus Fabric
• Up to 3 AHB Masters Can Be Accommodated
• Up to 16 AHB Slave Devices Are Supported
• Automatic Stitching to AHB Slaves and Masters in
CoreConsole
• Supports Swapping (or remapping) of Slave Slots 0
and 1 to Facilitate Processor Boot
Benefits
• Allows Easy Inter-Connection of AHB Masters and
Slaves in a Subsystem
• Devices Can Be Automatically Connected to
CoreAHB Using the Auto Stitch Feature in
CoreConsole, which Allows for Rapid System
Development
• Compatible with CoreMP7 and Cortex™-M1
Supported Device Families
• Fusion
• IGLOO™
• IGLOOe
• ProASIC^®3L
• ProASIC3
• ProASIC3E
General Description ................................................... 1
Arbitration Scheme .................................................... 2
Remapping ................................................................. 2
Connecting CoreAHB in CoreConsole ....................... 2
CoreAHB Port List ....................................................... 3
Resource Requirements ............................................. 5
Ordering Information ................................................ 5
List of Changes ........................................................... 6
Datasheet Categories ................................................. 6
General Description
CoreAHB implements a multi-master AHB bus fabric. Up
to 3 masters and 16 slaves can be connected to CoreAHB.
A block diagram of CoreAHB is shown in Figure 1. Each
AHB slave slot is allocated 256 megabytes of memory
space and all slave slots are accessible from each master
connection.
Master 1
Master 2
Master 3
Arbitration
Address
Decoder
Masters to Slaves
Mulitplexer
Slaves to Masters
Multiplexer
Slave 0
Slave 1
... ^{Slave 2}
Slave 15
Figure 1 • CoreAHB Block Diagram
Synthesis and Simulation Support
• Synthesis: Synplicity^®
• Simulation: ModelSim
Verification and Compliance
• Compliant with AMBA
January 2008
v2.1
1
© 2008 Actel Corporation