COREAES128 Datasheet, PDF (1/13 Pages) Actel Corporation – CoreAES128

CoreAES128
Product Summary
Intended Use
• Whenever Data is Transmitted Across an Accessible
Medium (Wires, Wireless, etc.)
• E-commerce Transactions Where Dedicated
Encryption/Decryption Hardware Can Ease the
Load on Servers
• Personal Security Devices
• Bank Transactions where State-of-the-Art
Financial Security Is Mandatory
Key Features
• Compliant with FIPS PUB 197
• ECB (Electronic Codebook) Implementation per
NIST SP 800-38A
• Example Source Code Provided for CBC, CFB, OFB,
and CTR Modes
• 128-bit Cipher Key
• Encryption and Decryption Possible with the Same
Core
• 44-Clock Cycle Operation to Encrypt or Decrypt
128 Bits of Data
• Pause/Resume Functionality to Continue
Encryption or Decryption at Will
• Provides Redundant Security
Supported Families
• Fusion
• ProASIC3/E
• ProASIC^PLUS®
• Axcelerator^®
Core Deliverables
• Evaluation Version
– Compiled RTL Simulation Model Fully
Supported in Actel Libero^® Integrated Design
Environment (IDE)
• Netlist Version
– Structural Verilog and VHDL Netlists (with and
without I/O Pads) Compatible with the Actel
Designer Software Place-and-Route Tool
– Compiled RTL Simulation Model Fully
Supported in Actel Libero IDE
• RTL Version
– Verilog and VHDL Core Source Code
– Core Synthesis Scripts
• Actel-Developed Testbench (Verilog and VHDL)
Synthesis and Simulation Support
• Synthesis: Synplicity^®, Synopsys^® (Design Compiler^®
/ FPGA Compiler™ / FPGA Express™), Exemplar™
• Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Core Verification
• Actel-Developed Simulation Testbench Verifies
CoreAES128 against Tests Available on the
National Institute of Standards and Technology
(NIST) Website:
http://csrc.nist.gov/encryption/aes/rijndael/
• User Can Easily Modify Testbench Using Existing
Format to Add Custom Tests
Contents
General Description ................................................... 2
CoreAES128 Device Requirements ............................ 4
CoreAES128 Verification ............................................ 4
I/O Signal Descriptions ............................................... 4
CoreAES128 Initialization .......................................... 4
CoreAES128 Operation .............................................. 4
Cipher Key Expansion ................................................ 6
Encryption .................................................................. 7
Decryption .................................................................. 8
Pause/Resume ............................................................. 9
Clear/Abort ............................................................... 10
Modes of Operation ................................................ 10
Ordering Information .............................................. 11
Export Restrictions ................................................... 11
List of Changes ......................................................... 12
Datasheet Categories ............................................... 12
December 2005
v4.0
1
© 2005 Actel Corporation