CORE429-XX Datasheet, PDF (1/22 Pages) Actel Corporation – ARINC 429 Bus Interface

ARINC 429 Bus Interface
Product Summary
Intended Use
• ARINC 429 Transmitter (Tx)
• ARINC 429 Receiver (Rx)
Key Features
• Supports ARINC Specification 429-16
• Configurable up to 16 Rx and 16 Tx Channels
• Programmable FIFO Depth
– Up to 512 Words
• Programmable Interrupt Generation
– Rx and Tx Channels independently
– Up to 64 Words
• Configurable Label Memory Size
– Rx and Tx Channels independently
– Up to 256 Words
• Internal, Wrap-Around Testing
• Software Compatible with Legacy Devices
• Selectable Clock Speed
– 1, 10, 16, or 20 MHz
• Selectable Data Rate on Each Channel
– 12.5 100 kbps
– Optional 50 kbps
• CPU Interface
– Provides Direct CPU Access to Memory
– Simple Interface to Core8051
• Memory
– EDAC Support with RTAX-S Family
• ARINC 429 Bus Interface
– Supports Standard Line Drivers and Receivers
• Available as Integrated Tx and Rx
Supported Families
• Fusion
• ProASIC^®3/E
• ProASIC^PLUS®
• Axcelerator^®
• RTAX-S
Core Deliverables
• Evaluation Version
– Compiled RTL Simulation Model, Compliant
with the Actel Libero^® Integrated Design
Environment (IDE)
• Netlist Version
– Structural VHDL and Verilog Netlists
• RTL version
– VHDL or Verilog Core Source Code
– Synthesis Scripts
• Verification Testbench – Verilog
• User Testbenches
– Libero IDE Compatible
– VHDL and Verilog
Development System
• Complete ARINC 429 Rx/Tx
• Implementation
– Implemented in an APA600 Device
– Controlled Via an External Terminal Using
Core8051 and RS232 Links
• Includes Line Driver and Receiver Components
Synthesis and Simulation Support
• Directly Supported within the Actel Libero IDE
• Synthesis:
– Synplicity®
– Exemplar^TM
– Synopsys^®
• Simulation
– Vital-Compliant VHDL Simulators
– OVI-Compliant Verilog Simulators
Verification and Compliance
• Actel-Developed Simulation Testbench
• Core Implemented on the ARINC 429
Development System
September 2006
v5.0
1
© 2006 Actel Corporation