APA1000-FG896A Datasheet, PDF (1/10 Pages) Actel Corporation – Automotive-Grade ProASIC Flash Family FPGAs

Automotive Supplement
TM
Automotive-Grade ProASIC^PLUS Flash Family FPGAs
Features and Benefits
High Capacity
• 75,000 to 1 Million System Gates
• 27k to 198kbits of Two-Port SRAM
• 66 to 642 User I/Os
Reprogrammable Flash Technology
• 0.22µ 4LM Flash-based CMOS Process
• Live at Power-Up, Single-Chip Solution
• No Configuration Device Required
• Retains Programmed Design during
Power-Down/Power-Up Cycles
Extended Temperature Range
• Supports Automotive Temperature Range -40 to 125°C (Junction)
Performance
• 3.3V, 32-Bit PCI (up to 50 MHz)
• Two Integrated PLLs
• External System Performance up to 150 MHz
Secure Programming
• Industry’s Most Effective Security Key (FlashLock™)
Prevents Read Back of Programming Bitstream
Low Power
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
• Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
High Performance Routing Hierarchy
• Ultra-Fast Local and Long-Line Network
Table 1 • Automotive-Grade ProASIC^PLUS Product Profile
• High-Speed, Very Long-Line Network
• High Performance, Low-Skew, Splittable Global Network
• 100% Utilization and >95% Routability
I/O
• Schmitt-Trigger Option on Every Input
• 2.5V/3.3V Support with Individually-Selectable Voltage and
Slew Rate
• Bidirectional Global I/Os
• Compliance with PCI Specification Revision 2.2
• Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
• Pin Compatible Packages across ProASIC^PLUS Family
Unique Clock Conditioning Circuitry
• PLLs with Flexible Phase, Multiply/Divide and Delay
Capabilities
• Internal and/or External Dynamic PLL Configuration
• Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
• Flexibility with Choice of Industry-Standard Frontend Tools
• Efficient Design through Front-End Timing and Gate
Optimization
ISP Support
• In-System Programming (ISP) via JTAG Port
SRAMs and FIFOs
• ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
• 24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
Device
APA075 APA150 APA300 APA450
APA600 APA750 APA1000
Maximum System Gates
75,000 150,000 300,000
450,000
600,000 750,000 1,000,000
Maximum Tiles (Registers)
3,072
6,144
8,192
12,288
21,504
32,768 56,320
Embedded RAM Bits (k=1,024 27k
36k
72k
bits)
108k
126k
144k
198k
Embedded RAM Blocks (256x9)
12
16
32
48
56
64
88
LVPECL
2
2
2
2
2
2
2
PLL
2
2
2
2
2
2
2
Global Networks
4
4
4
4
4
4
4
Maximum Clocks
24
32
32
48
56
64
88
Maximum User I/Os
158
186
186
344
370
562
642
JTAG ISP
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Package (by pin count)
TQFP
100
100
–
–
–
–
–
PQFP
208
208
208
208
208
208
208
FBGA
144
144, 256 144, 256 144, 256, 484 256, 484
896
896
February 2004
1
© 2004 Actel Corporation