A54SX16-2 Datasheet, PDF (1/4 Pages) Actel Corporation – PCI Arbiter Core

v4.0
PCI Arbiter Core
Features
• Support for up to Five PCI Bus Masters
• Support for Two Arbitration Schemes
– Pure Rotation
– Fair Rotation
• Support for Bus Parking
• Hidden Bus Arbitration
• Interface with 33 MHz and 66 MHz PCI Systems
• Implementation in Actel’s SX, SX-A, ProASIC and
ProASIC^PLUS Families
• Synthesizable VHDL Source Code
• Device Utilization
– SX/SX-A 100-150 Modules
– ProASIC/ProASIC^PLUS 124-135 Tiles
General Description
The Arbiter core is used to efficiently manage access to a
PCI bus that is shared by several masters. Access to the PCI
bus is automatically determined by the individual priorities
of each master.
In the most common application, customers use an
embedded processor as the master with highest priority and
a pure-rotation arbitration scheme among other PCI bus
masters. The networking and telecom markets are the
targets for this macro.
Implementation
At any given time, more than one PCI bus initiator (Master)
device may request use of the PCI bus by asserting its
specific request signal (REQn). The Arbiter determines
which PCI bus initiator controls the PCI bus by asserting
that device’s specific grant signal (GNTn). Figure 1 shows
the PCI Arbiter Core interface signals and Figure 2
illustrates the relationship of the PCI bus initiator devices
with the Arbiter.
PCI_CLK
RSTn
FRAMEn
IRDYn
REGn(4:0)
GNTn(4:0)
Figure 1 • PCI Arbiter Core Interface Signals
PCI Device 1
REQn1
GNTn1
PCI Device 2
GNTn2
REQn2
PCI Device 3
GNTn3
REQn3
PCI Device 0
REQn0
GNTn0
PCI Arbiter
GNTn4
REQn4
PCI Device 4
RSTn
CLK
IRDYn
FRAMEn
Figure 2 • Top-Level Interface of the PCI Bus Initiators with the Arbiter
January 2002
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© 2002 Actel Corporation