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A3P1000-1FGG144T Datasheet, PDF (1/136 Pages) Actel Corporation – Automotive ProASIC3 Flash Family FPGAs | |||
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v1.0
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Automotive ProASIC3 Flash Family FPGAs
Features and Benefits
High-Temperature AEC-Q100âQualified Devices
⢠Grade 2 105°C TA (115°C TJ)
⢠Grade 1 125°C TA (135°C TJ)
⢠PPAP Documentation
Firm-Error Immune
⢠Only Automotive FPGAs to Offer Firm-Error Immunity
⢠Can Be Used without Configuration Upset Risk
High Capacity
⢠60 k to 1 M System Gates
⢠Up to 144 kbits of SRAM
⢠Up to 300 User I/Os
Reprogrammable Flash Technology
⢠130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
⢠Live-at-Power-Up (LAPU) Level 0 Support
⢠Single-Chip Solution
⢠Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
⢠1 kbit of FlashROM with Synchronous Interface
High Performance
⢠350 MHz System Performance
⢠3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
⢠Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532âcompliant)
⢠FlashLock® to Secure FPGA Contents (anti-tampering)
Automotive ProASIC3 Product Family
Low Power
⢠1.5 V Core Voltage
⢠Support for 1.5-V-Only Systems
⢠Low-Impedance Flash Switches
High-Performance Routing Hierarchy
⢠Segmented, Hierarchical Routing and Clock Structure
⢠High-Performance, Low-Skew Global Network
⢠Architecture Supports Ultra-High Utilization
Advanced I/O
⢠700 Mbps DDR, LVDS-Capable I/Os
⢠1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
⢠Bank-Selectable I/O Voltagesâup to 4 Banks per Chip
⢠Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
⢠Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and A3P1000)
⢠I/O Registers on Input, Output, and Enable Paths
⢠Hot-Swappable and Cold-Sparing I/Os
⢠Programmable Output Slew Rate and Drive Strength
⢠Weak Pull-Up/-Down
⢠IEEE 1149.1 (JTAG) Boundary Scan Test
⢠Pin-Compatible Packages across the Automotive ProASIC®3
Family
Clock Conditioning Circuit (CCC) and PLL
⢠Six CCC Blocks, One with an Integrated PLL
⢠Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
⢠Wide Input Frequency Range (1.5 MHz up to 350 MHz)
SRAMs
⢠Variable-Aspect-Ratio 4,608-Bit RAM Blocks (Ã1, Ã2, Ã4, Ã9,
and Ã18 organizations available)
ProASIC3 Devices
A3P060
A3P125
A3P250
A3P1000
System Gates
60 k
125 k
250 k
1M
VersaTiles (D-flip-flops)
1,536
3,072
6,144
24,576
RAM kbits (1,024 bits)
18
36
36
144
4,608-Bit Blocks
4
8
8
32
FlashROM Bits
1k
1k
1k
1k
Secure (AES) ISP
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
1
1
1
1
VersaNet Globals*
18
18
18
18
I/O Banks
2
2
4
4
Maximum User I/Os
96
133
157
300
Package Pins
VQFP
FBGA
VQ100
FG144
VQ100
FG144
VQ100
FG144, FG256
FG144, FG256, FG484
Note: *Six chip-wide (main) globals and three additional global networks in each quadrant are available.
January 2008
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© 2008 Actel Corporation
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