ACE24C02A Datasheet, PDF (7/14 Pages) ACE Technology Co., LTD. – Two-wire Serial EEPROM

Technology
ACE24C02A
Two-wire Serial EEPROM
Figure 4．Data Validity
Figure 5．Start and Stop Definition
Figure 6．Output Acknowledge
Device Addressing
The 2K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (refer to Figure 7).
The device address word consists of a mandatory one, zero sequence for the first four most
significant bits as shown. This is common to all the EEPROM devices. The next 3 bits can be any
data.
The module package device address word also consist of a mandatory one, zero sequence for the
first four most significant bits. The next 3 bits are all zero.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the
chip will return to a standby state.
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