ACE25C800G Datasheet, PDF (6/37 Pages) ACE Technology Co., LTD. – Uniform SECTOR Dual and Quad Serial Flash

ACE25C800G
Uniform SECTOR Dual and Quad Serial Flash
Data Protection
The ACE25C800G provide the following data protection methods:
 Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL).
The WEL bit will return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register(WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
 Software Protection Mode: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section
of the memory array that can be read but not change.
 Hardware Protection Mode: WP# going low to protected the BP0~SEC bits and SRP0~1 bits.
 Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the
Release from deep Power-Down Mode command.
Table1.0 ACE25C800G Protected area size (CMP=0)
Status Register Content
Memory Content
SEC TB BP2 BP1 BP0 Blocks
Addresses
Density
XX0
0
0 NONE
NONE
NONE
000
0
1
15
0F0000H-0FFFFFH 64KB
000
1
0 14 to 15 0E0000H-0FFFFFH 128KB
000
1
1 12 to 15 0C0000H-0FFFFFH 256KB
001
0
0 8 to 15 080000H-0FFFFFH 512KB
010
0
1
0
000000H-00FFFFH 64KB
010
1
0
0 to 1 000000H-01FFFFH 128KB
010
1
1
0 to 3 000000H-03FFFFH 256KB
011
0
0
0 to 7 000000H-07FFFFH 512KB
0X1
0
1 0 to 15 000000H-0FFFFFH
1M
XX1
1
X 0 to15 000000H-0FFFFFH
1M
100
0
1
15
0FF000H-0FFFFFH
4KB
100
1
0
15
0FE000H-0FFFFFH
8KB
100
1
1
15
0FC000H-0FFFFFH 16KB
101
0
X
15
0F8000H-0FFFFFH 32KB
110
0
1
0
000000H-000FFFH
4KB
110
1
0
0
000000H-001FFFH
8KB
110
1
1
0
000000H-003FFFH 16KB
111
0
X
0
000000H-007FFFH 32KB
Portion
NONE
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
ALL
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
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