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| ACE306A Datasheet, PDF (4/8 Pages) ACE Technology Co., LTD. – Low Voltage Detector with Built-in Delay Circuit | |||
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ACE306A
Low Voltage Detector with Built-in Delay Circuit
0.5V
VDD=-VDET ACE306A C/N39~60
1.5
8.0
+0.5V
-
mA
ILEAK
Leakage
Current
Only for NMOS open-drain output
products, VDD =8.0 V, VOUT =8.0 V
Temperature
Coefficient
Ta=â40°C ~+85°C
-
-
±120
1.0
μA
±360 ppm/°C
TPLH
Delay time
Vin=Vdet+0.5V
130
210
290
ms
*1. âVDET: Actual detection voltage value, âVDET(S): Specified detection voltage value
Function description
When a voltage higher than the release voltage (+VDET) is applied to the voltage input pin (VDD), the
voltage will gradually fall. When a voltage higher than the detect voltage(-VDET) is applied to VDD, output
(VOUT) will be equal to the input at VDD.Note that high impedance exists at VOUT with the N-channel open
drain configuration. If the pin is pulled up, VOUT T will be equal to the pull up voltage.
When VDD falls below -VDET, VOUT will be equal to the ground voltage (VSS) level (detect state). Note that
this also applies to N-channel open drain configurations.
When VDD falls to a level below that of the minimum operating voltage (VMIN) output will become unstable.
Because the output pin is generally pulled up with N-channel open drain configurations, output will be
equal to pull up voltage.
When VDD rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT
will be equal to VSS until VDD reaches the +VDET level.
Although VDD will rise to a level higher than +VDET, VOUT maintains ground voltage level via the delay
circuit.
Following transient delay time, VDD will be output at VOUT. Note that high impedance exists with the
N-channel open drain configuration and that voltage will be dependent on pull up
VER 1.1 4
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