ACE24AC512 Datasheet, PDF (3/16 Pages) ACE Technology Co., LTD. – Two-wire Serial EEPROM

Block Diagram
ACE24AC512
Two-wire Serial EEPROM
Pin Descriptions
(A) Serial Clock (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
(B) Device / Chip Select Addresses (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
hardwired to either V_IH or V_IL. If left unconnected, they are internally recognized as V_IL.
(C) Serial Data Line (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
(D) Write Protect (WP)
The ACE24AC512 devices have a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to V_IL. Conversely all
programming functions are disabled if WP pin is connected to V_IH or V_CC. Read operations is not
affected by the WP pin’s input level.
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