AK63264BZ_09 Datasheet, PDF (1/2 Pages) ACCUTEK MICROCIRCUIT CORPORATION – Static Random Access Memory

ACCUTEK
MICROCIRCUIT CORPORATION
AK63264BZ
65,536 x 32 Bit CMOS/BiCMOS
Static Random Access Memory
DESCRIPTION
The Accutek AK63264BZ SRAM Module consists of fast high
performance SRAMs mounted on a low height, 64 pin SIM or ZIP
Board. The module utilizes four 32 pin 64K x 8 SRAMs in 300 mil
SOJ packages and four decoupling capacitors mounted on the front
side of a printed circuit board.
The SRAMs used have common I/O functions and single output en-
able functions. Also, four separate chip select (CE) connections are
used to independently enable the four bytes. The modules can be
supplied in a variety of access time values from 12nSEC to 35nSEC
in CMOS or BiCMOS technology.
The Accutek module is designed to have a maximum seated height
of 0.520 inch to provide for the lowest height off the board. Each
conforms to JEDEC-standard sizes and pin-out configurations.
Using two pins for module density identification, PD₀ and PD₁, mini-
mizes interchangeability and design considerations when changing
from one module size to the other in customer applications.
FEATURES
· 65,536 x 32 bit organization
· JEDEC Standard 64 pin ZIP format
· Common I/O, single OE fucntions with four separate chip se-
lects (CE)
· Low height 0.520 inch maximum
· Presence Detect, PD₀ and PD₁ for identifying module density
· Downard compatible with 32K x 32 (AK63232)
· Fast access times from 12nSEC
Front View
1
32 33
64
· Upward compatible with 128K x 32 (AK632128), 256K x 32
(AK632256), 512K x 32 (AK632512) and 1 Meg x 32
(AK6321024)
· TTL-compatible inputs and outputs
· Single 5 volt power supply - AK63264BZ
· Single 3.3 volt power supply - AK63264BZ/3.3
· Operating temperature range in free air, 0⁰ to 70⁰C
ELECTRICAL SPECIFICATIONS
Timing Diagrams and basic electrical characteristics are those of
the standard 64K x 8 SRAMs used to construct these modules.
Accutek’s module design allows the flexibility of selecting indus-
try-compatible 64K x 8 SRAMs from several semiconductor manu-
facturers.
PIN NOMENCLATURE
PIN ASSIGNMENT
FUNCTIONAL DIAGRAM
A0 - A15
CE1 - CE4
DQ1 - DQ32
OE
PD0 - PD1
Vcc
Vss
WE
NC
Address Inputs
Chip Enable
Data In/Data Out
Output Enable
Presence Detect
Power Supply
Ground
Write Enable
No Connect
MODULE OPTIONS
Leaded ZIP: AK63264BZ
PIN # SYMBOL PIN # SYMBOL PIN # SYMBOL PIN # SYMBOL
1 Vss 17 A2 33 CE4 49 A4
2 PD0 18 A9 34 CE3 50 A11
3 PD1 19 DQ13 35 NC 51 A5
4 DQ1 20 DQ5 36 NC 52 A12
5 DQ9 21 DQ14 37 OE 53 Vcc
6 DQ2 22 DQ6 38 Vss 54 A13
7 DQ10 23 DQ15 39 DQ25 55 A6
8 DQ3 24 DQ7 40 DQ17 56 DQ21
9 DQ11 25 DQ16 41 DQ26 57 DQ29
10 DQ4 26 DQ8 42 DQ18 58 DQ22
11 DQ12 27 Vss 43 DQ27 59 DQ30
12 Vcc 28 WE 44 DQ19 60 DQ23
13 A0 29 A15 45 DQ28 61 DQ31
14 A7 30 A14 46 DQ20 62 DQ24
15 A1 31 CE2 47 A3 63 DQ32
16 A8 32 CE1 48 A10 64 Vss
PD0 = Open
PD1 = Vss