ALVD Datasheet, PDF (2/3 Pages) Abracon Corporation – CERAMIC SMD CRYSTAL CLOCK OSCILLATOR WITH VOLTAGE CONTROL

CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
ALVD
Pb
RoHS
Compliant
LVDS:
Supply current (I_DD):25mA max (for Fo<24MHz),45mA max (for 24MHz<Fo<96MHz),80mA max (96MHz<Fo<700MHz)
Output Clock Duty Cycle @ 1.25V: 45% min, 50% typical, 55% max
Output Differential Voltage (V_OD): 247mV min, 355mV typical, 454mV max
VDD Magnitude Change (ΔV_OD): -50mV min, 50mV max
Output High Voltage : V_OH = 1.4V typical, 1.6V max.
Output Low Voltage: V_OL = 0.9V min, 1.1V typical
Offset Voltage [R_L = 100Ω]: V_OS = 1.125V min, 1.2V typical, 1.375V max
Offset Magnitude Change [R_L = 100Ω]: ΔV_OS = 0mV min, 3mV typical, 25mV max
Power-off Leakage (I_OXD) [Vout=VDD or GND, VDD=0V] = ±1μA typical, ±10μA max.
Differential Clock Rise Time (t_r) [R_L=100Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS,max
Differential Clock Fall Time (t _f) [R_L=100Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS max
PIN ASSIGNMENTS
PIN #
Name
1
Vc
2
Tristate
3
GND
4
Q
5
Q
6
V_DD
DESRIPTION
Voltage Control
Tristate
Ground
PECL, LVDS, or CMOS Output.
Complimentary PECL,LVDS, or NC.
VDD Connection.
TRI-STATE PIN OPERATION:
OUTPUT TYPE
OPTION
PIN 2 logic level*
Output State (Tri-state)
P
PECL
0 (Default)
1
Enabled
Disabled
P1
PECL1
0
1
Disabled
Enabled
V
LVDS
0
1(Default)
Disabled
Enabled
C
CMOS
0
1(Default)
Disabled
Enabled
*Connect to VDD for logic level "1", connect to ground for logic level "0".
7.0 x 5.0 x 1.8mm
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OPTIONS & PART IDENTIFICATION:
(Left blank if standard)
ALVD - Frequency - - - - -
Frequency
XX.XXXXMHz
Operating Temp.
D
-10ºC~60ºC
E
-20ºC~70ºC
F
-30ºC~70ºC
N
-30ºC~85ºC
L
-40ºC~85ºC
Frequency Stability
R
±25ppm max.
K
±30ppm max.
H
±35ppm max.
Output Level
P
PECL
P1
PECL1
V
LVDS
C
CMOS
Packaging
Blank
Bulk
T
Tape and
Reel
Pullability
N100 ±100ppm
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
Visit www.abracon.com for Terms & Conditions of Sale Revised: 07.11.07
30332 Esperanza, Rancho Santa Margarita, California 92688
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