ASG-ULJ Datasheet, PDF (1/5 Pages) Abracon Corporation – Backplane reference clock

Ultra Low Jitter SMD Crystal Oscillator
ASG-ULJ
Moisture Sensitivity Level (MSL) – 1
FEATURES:
• Ultra low phase Jitter: 0.2ps max integrated 12 kHz to 20 MHz BW
• ±50ppm total frequency stability over -40°C to +85°C temperature range
• Output type: LVCMOS, LVPECL, LVDS
• Industry standard ceramic SMD package: 7.0 x5 .0mm
Pb
RoHS
Compliant
APPLICATIONS:
7.0 x 5.0 x 1.5 mm
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• Fiber Channel 10G/12G SERDES
• 10/40/400 Gigabit Ethernet
• PCI-Express
• Storage
• Communications
• Backplane reference clock
• FPGA
STANDARD SPECIFICATIONS:
Key Electrical Specifications
Parameters
Minimum Typical Maximum Units
Notes
Operating Temperature
-40
+85
°C
Storage Temperature
-55
+125
°C
Overall Frequency Stability
-50
+50
ppm
See Note # 1
Initial Tolerance + Stability over
operating temperature
-35.00
+35.00
ppm
Supply Voltage (Vdd)
V_dd = 3.3V
V_dd = 2.5V
3.135
2.375
3.300
2.500
3.465
V
2.625
V
Enable/Disable Function :
"1" (V_IH ≥ 0.7*Vdd) or Open: Oscillation
"0" (V_IL < 0.3*Vdd) : High Z
Phase jitter RMS (12kHz to 20MHz BW)
0.2
ps
at 25ºC
Note #1: Inclusive of initial tolerance at 25ºC±3ºC, operating temperature range, input voltage variation, load variation & 10 years
aging at 25ºC.
Key Electrical Specifications – LVCMOS
Parameters
Frequency Range
Supply Current (I_dd)
Output Logic Level
Rise Time
Fall Time
Duty Cycle
Output Load
Minimum
1
V_OH
0.9*V_dd
V_OL
Tr
Tf
45
Typical
50
Maximum
200
40
0.1*V_dd
3
3
55
15
Units
MHz
mA
V
V
ns
ns
%
pF
Notes
I=±6mA
10% to 90%
Key Electrical Specifications – LVDS
Parameters
Frequency Range
Supply Current (I_dd)
Differential Output Voltage Swing
Duty Cycle
Rise Time
Tr
Fall Time
Tf
Minimum
1
45
Typical
350
Maximum
705.8
80
55
0.6
0.6
Units
MHz
mA
mV
%
Notes
Freq. dependent
@1.25V
ns RL=100Ω/CL=10pF
ABRACON IS
ISO9001:2008
CERCTEIFRIETDIFIED
5101 Hidden Creek Lane Spicewood TX 78669
Phone: [phone] | Fax: [phone]
Revised: 07.26.2016
LLC
For terms and conditions of sale please visit:
www.abracon.com