ASDMP-2D Datasheet, PDF (1/1 Pages) Abracon Corporation – VOLTAGE CONTROLLED TEMP

0.098 ±0.002
2.50 ±0.05
6
5
4
0.032
0.825
4
5
6
Via to GND
Layer
Via to Power Layer
0.015
0.375
1
2
3
3
0.026 ±0.00
0.65 ±0
2
1
0.010 ±0.005
0.25 ±0.13
6
5
4
1
2
3
Via to GND Layer
Via to Power Layer
2
4
1
3
0.026
0.65
Recommended Land Pattern FOR CMOS
NOTE: Recommended using approximately
0.01uf bypass capacitor between PIN 6 and 3
0.03
0.65
Recommended Land Pattern FOR LVPECL,LVDS,HCSL
Pin
Function
1
Tri-state
2
NC
3
GND
4
Output
5
NC (CMOS) Output
(LVPECL, LVDS, HCSL)
6
Vdd
UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE IN INCH(MM)
SURFACE FINISH:
TOLERANCES:
LINEAR:
ANGULAR:
FINISH:
DRAWN
CHK'D
APPV'D
MFG
Q.A
NAME
XXXXXX
XXXXXX
SIGNATURE
DATE
MATERIAL:
WEIGHT:
DEBUR AND
BREAK SHARP
EDGES
DO NOT SCALE DRAWING
REVISION
-
30332 Esperanza, Rancho Santa margarita, California 92688
TITLE: _{VOLTAGE CONTROLLED TEMP. COMPENSATED}
SMD CRYSTAL OSCILLATOR
DWG NO.
ASDMP
A3
SCALE:10:1
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