APVV Datasheet, PDF (1/2 Pages) Abracon Corporation – CERAMIC SMD VOLTAGE CONTROL CRYSTAL OSCILLATOR

CERAMIC SMD VOLTAGE CONTROL CRYSTAL OSCILLATOR
APVV SERIES : PRELIMINARY
FEATURES:
• CMOS, PECL or LVDS Output
• Sub 1pS ( 12kHz - 20MHz )
• Low Jitter
• Low Power ( 2.5, 3.3V )
• Wide Pull Range
APPLICATIONS:
5.0 x 7.0 x 1.8mm
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• SONET, Fiber Channel, SERDES
HDTV, OBSAI, CPRI, PCI Express, 1394
STANDARD SPECIFICATIONS: PARAMETERS
Frequency Range
38 MHz to 640 MHz
Operating Temperature
0°C to + 70°C (see options)
Storage Temperature
-55°C to +125°C
Frequency Pull Range
± 50 ppm (see options)
Pull Range Linearity
10% Max
Overall Frequency Stability ± 50 ppm max. (see options)
Supply Voltage (Vdd)
2.25V to 3.63 (2.5V to 3.3V ± 10%)
Phase Jitter RMS (12KHz-20MHz) 0.5pS Typ, 1pS Max
Period Jitter (peak to peak) 20pS typ., 30pS max up to 320 MHz; 50pS typ., 70pS max 321MHz to 640MHz
Tri-State Function
PECL
Supply Current (I_DD)
Symmetry (Duty Cycle)
For CMOS and LVDS = "1" (VIH ³ 0.7* Vdd) or open: Oscillation;
"0" (VIL < 0.3* Vdd): No oscillation/Hi Z
For PECL (See TriState Pin Operation table) = P Option (Standard PECL OE)
"0" (VIL < 0.3* Vdd): or Open: Oscillation; "1" (VIH ³ 0.7* Vdd): No oscillation/Hi Z
P1 Option = "1" (VIH ³ 0.7* Vdd) or open: Oscillation;
"0" (VIL < 0.3* Vdd): No oscillation/Hi Z
65mA max (for 38MHz<Fo<320MHz), 90mA max (320MHz<Fo<640MHz)
45% min, 50% typical, 55% max.
Output Logic High
Output Logic Low
Rise time
V_DD -1.025V min, V_DD -0.880V max.
V_DD -1.810V min, V_DD -1.620V max.
1.5ns max, 0.6nSec typical
Fall time
1.5ns max, 0.6nSec typical
CMOS
Supply Current
30mA max (38MHz<Fo<320MHz)
Symmetry (Duty Cycle)
45% min, 50% typ, 55% max,
Rise/ Fall Time
(0.3V ~ 3.0V w/15 pF load) 0.7nS Typ.; (20%-80% w/50Ω Load) 0.3nS Typ.
LVDS
Supply Current (I_DD)
Output Clock Duty Cycle @ 1.25V
45mA max(for 38MHz<Fo<320MHz), 70mA max (320MHz<Fo<640MHz)
45% min, 50% typical, 55% max
Output Differential Voltage (V_OD)
VDD Magnitude Change (∆V_OD)
Output High Voltage
Output Low Voltage
Offset Voltage [R_L = 100Ω]
Offset Magnitude Voltage[RL = 100Ω]
Power-off Leakage (I_OXD) [Vout=VDD or GND, VDD=0V]
Differential Clock Rise Time (t_r) [R_L=100Ω, CL=10pF]
Differential Clock Fall Time (t_f) [R_L=100Ω, CL=10pF]
247mV min, 355mV typical, 454mV max
-50mV min, 50mV max
V_OH = 1.6V max, 1.4V typical
V_OL = 0.9V min, 1.1V typical
V_OS = 1.125V min, 1.2V typical, 1.375V max
∆V_OS = 0mV min, 3mV typical, 25mV max
±10µA max, ±1µA typical
0.7ns typical, 1.0ns max
0.7ns typical, 1.0ns max
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
30332 Esperanza, Rancho Santa Margarita, California 92688
tel [phone] | fax [phone] | www.abracon.com