AD8275_10 Datasheet, PDF (11/16 Pages) Aavid, Thermal Division of Boyd Corporation – G = 0.2, Level Translation, 16-Bit ADC Driver

AD8275
THEORY OF OPERATION
The AD8275 level translates ±10 V signals at its inputs to 4 V
at its output. It does this by attenuating the input signal by 5.
A subtractor network performs the attenuation, the level shifting,
and the differential-to-single-ended conversion. One benefit of
the subtractor topology is that it can accept input signals
beyond its supply voltage. The subtractor is composed of tightly
matched resistors. By integrating the resistors and trimming the
resistor ratios, the AD8275 achieves 80 dB CMRR and 0.024%
gain error.
–IN
INPUT ^50kΩ
ESD
10kΩ
+V_S
SENSE
+V_S
–V_S
–V_S
+V_S
7kΩ
+V_S
7kΩ
OUT
2.5V
–V_S
–V_S
–V_S
+V_S
–V_S
+V_S
20kΩ
REF2
+IN
INPUT
ESD _50kΩ
–V_S
+V_S
20kΩ
REF1
–V_S
Figure 31. AD8275 Simplified Schematic
To achieve a wider input voltage range, the AD8275 uses an
internal 2.5 V voltage bias tied to –VS and two 7 kΩ resistors, as
shown in Figure 31. The resistors help to set the common mode
of the internal amplifier. The benefit of this circuit is that it
extends the input range without causing crossover distortion
typical of amplifiers that have rail-to-rail complementary
transistor inputs. The input range of the internal op amp is
+VS − 0.9 V to −VS + 1.35 V.
600
400
200
0
–200
–400
–600
–10 –8 –6 –4 –2 0 2 4 6
COMMON-MODE VOLTAGE (V)
8 10
Figure 32. AD8275 Does Not Have Crossover Distortion Typical of Rail-to-Rail
Input Amplifiers
The AD8275 employs a balanced, high gain, linear output stage
that adaptively generates current as required, eliminating the
dynamic errors found in other amplifiers. This is useful when
driving SAR ADCs, which can deliver kickback current into the
output of the amplifier. The result is a design that achieves low
distortion, consistent bandwidth, and high slew rate.
BASIC CONNECTION
The basic configurations for the AD8275 are shown in
Figure 33 and Figure 34. In Figure 33, REF1 and REF2 are
tied together. A voltage, VREF, applied to the tied REF1 and
REF2 pins, sets the output voltage level to VREF. For example,
in Figure 33, if VREF = 2 V and the inputs are tied to ground,
the output remains at 2 V.
+5V
0.1µF
50kΩ
V_INN
2
–IN
7
+V_S
10kΩ
5
SENSE
OUT
6
50kΩ
V_INP 3
+IN
20kΩ
8
REF2
20kΩ
1
REF1
AD8275 –VS
4
V_OUT
V_REF
V_OUT =
(V_INP) – (V_INN)
5
+ V_REF
Figure 33. Basic Configuration 1: Shared Reference
In contrast, Figure 34 shows REF1 tied to ground and REF2
tied to VREF. In this example, the two 20 kΩ resistors serve as a
resistor divider, and VREF is divided by 2. For example, if both
inputs of the AD8275 are grounded and VREF = 5 V, the output
is 2.5 V.
+5V
0.1µF
V_INN
50kΩ
2
–IN
7
+V_S
10kΩ
5
SENSE
OUT
6
V_INP
50kΩ
3
+IN
20kΩ
8
REF2
20kΩ
1
REF1
AD8275 –VS
4
V_OUT
V_REF
V_OUT =
(V_INP) – (V_INN)
5
+
V_REF + 0V
2
Figure 34. Basic Configuration 2: Split Reference
Rev. A | Page 11 of 16