AAT1155 Datasheet, PDF (12/17 Pages) Advanced Analogic Technologies – 1MHz 2.5A Step-Down DC/DC Converter

AAT1155
1MHz 2.5A Step-Down DC/DC Converter
A high ESR tantalum capacitor with a value about 10
times the input ceramic capacitor may also be
required when using a 10µF or smaller ceramic input
bypass capacitor. This dampens any input oscilla-
tions that may occur due to the source inductance
resonating with the converter input impedance.
Output Capacitor
With no external compensation components, the out-
put capacitor has a strong effect on the loop stability.
Larger output capacitance will reduce the crossover
frequency with greater phase margin. A 200µF
ceramic capacitor provides sufficient bulk capacitance
to stabilize the output during large load transitions and
has ESR and ESL characteristics necessary for very
low output ripple. The RMS ripple current is given by:
I_RMS =
1
2·
3
·(V^{OUT+VFWD) ·(VIN}
L · F · V_IN
-
V_OUT)
For a ceramic output capacitor, the dissipation due
to the RMS current and associated output ripple
are negligible.
Tantalum capacitors with sufficiently low ESR to
meet output ripple requirements generally have an
RMS current rating much greater than that actually
seen in this application. The maximum tantalum
output capacitor ESR is:
ESR ≤ ^VRIPPLE
∆I
where ∆I is the peak-to-peak inductor ripple current.
Due to the ESR zero associated with the tantalum
capacitor, smaller values than those required with
ceramic capacitors provide more phase margin
with a greater loop crossover frequency.
Layout
Figures 3 and 4 display the suggested PCB layout
for the AAT1155. The following guidelines should
be used to help ensure a proper layout.
1. The connection from the input capacitor to the
Schottky anode should be as short as possible.
2. The input capacitor should connect as closely
as possible to V_P (Pins 5 and 8) and GND
(Pin 2).
3. C1, L1, and CR1 should be connected as
closely as possible. The connection from the
cathode of the Schottky to the LX node
should be as short as possible.
4. The feedback trace (Pin 1) should be separate
from any power trace and connect as closely
as possible to the load point. Sensing along a
high-current load trace can degrade DC load
regulation.
5. The resistance of the trace from the load
return to the ground (Pin 2) should be kept to
a minimum. This will help to minimize any
error in DC regulation due to differences in
the potential of the internal reference ground
and the load return.
6. R1 and C3 are required in order to provide
a cleaner power source for the AAT1155 con-
trol circuitry.
Figure 3: Evaluation Board Top Side.
12
Figure 4: Evaluation Board Bottom Side.
1155.2005.11.1.6