AAT1151 Datasheet, PDF (10/16 Pages) Advanced Analogic Technologies – 850kHz 700mA Synchronous Buck DC/DC Converter

AAT1151
850kHz 700mA Synchronous Buck DC/DC Converter
Input Capacitor
The primary function of the input capacitor is to pro-
vide a low impedance loop for the edges of pulsed
current drawn by the AAT1151. A low ESR/ESL
ceramic capacitor is ideal for this function. To mini-
mize stray inductance, the capacitor should be
placed as close as possible to the IC. This keeps the
high frequency content of the input current localized,
minimizing radiated and conducted EMI while facili-
tating optimum performance of the AAT1151.
Ceramic X5R or X7R capacitors are ideal for this
function. The size required will vary depending on the
load, output voltage, and input voltage source imped-
ance characteristics. A typical value is around 10µF.
The input capacitor RMS current varies with the input
voltage and the output voltage. The equation for the
RMS current in the input capacitor is:
I_RMS = I_O ·
V_{O ·} ⎛_{1 -} V_O ⎞
V_IN ⎝
V_IN ⎠
The input capacitor RMS ripple current reaches a
maximum when V_IN is two times the output voltage
where it is approximately one half of the load cur-
rent. Losses associated with the input ceramic
capacitor are typically minimal and are not an issue.
Proper placement of the input capacitor can be seen
in the reference design layout in Figures 2 and 4.
Output Capacitor
Since there are no external compensation compo-
nents, the output capacitor has a strong effect on
loop stability. Lager output capacitance will reduce
the crossover frequency with greater phase mar-
gin. For the 1.5V 1A design using the 4.1µH induc-
tor, two 22µF capacitors provide a stable output. In
addition to assisting stability, the output capacitor
limits the output ripple and provides holdup during
large load transitions. The output capacitor RMS
ripple current is given by:
I_RMS =
1
2·
·
3
V_OUT · (V_IN - V_OUT)
L · F · V_IN
For a ceramic capacitor, the ESR is so low that dis-
sipation due to the RMS current of the capacitor is
not a concern. Tantalum capacitors with sufficiently
low ESR to meet output voltage ripple require-
ments also have an RMS current rating well
beyond that actually seen in this application.
Layout
Figures 2 through 5 display the suggested PCB
layout for the AAT1151. The following guidelines
should be used to help ensure a proper layout.
• The input capacitor (C1) should connect as
closely as possible to V_POWER (Pin 5) and
P_GND (Pin 8).
• C2 and L1 should be connected as closely as
possible. The connection L1 to the LX node
should be as short as possible.
• The feedback trace (Pin 1) should be sepa-
rate from any power trace and connect as
closely as possible to the load point. Sensing
along a high-current load trace will degrade
DC load regulation.
• The resistance of the trace from the load
return to the PGND (Pin 8) should be kept to
a minimum. This will help to minimize any
error in DC regulation due to differences in
the potential of the internal signal ground
and the power ground.
• Low pass filter R1 and C3 provide a cleaner
bias source for the AAT1151 active circuitry.
C3 should be placed as closely as possible
to SGND (Pin 2) and V_CC (Pin 4). See
Figures 2 and 7.
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1151.2005.11.1.4