IMP5245 Datasheet, PDF (1/5 Pages) A1 PROs co., Ltd. – LVD SCSII Termiinattor

IMP5245/46
DATA COMMUNICATIONS
LVD SCSI Terminator
– Ultra2/3 SCSI
– 9 Channels
– Eliminates External V_REF Capacitor
The IMP5245/5246 ICs are Low Voltage Differential (LVD) terminators
designed to comply with the LVD termination specification in the SPI-2
document. The IMP5245/5246 are designed specifically for LVD appli-
cations. Because the IMP5245/5246 support only LVD, they have lower
output capacitance than multimode terminators.
The IMP5245/5246 deliver the ultimate in SCSI bus performance while
saving component cost and board area. Elimination of the external
capacitors also mitigates the need for a lengthy capacitor selection
process. The individual high bandwidth drivers also maximize channel
separation and reduces channel-to-channel noise and cross talk. The
high-bandwidth architecture insures ULTRA-2 performance, while pro-
viding a clear migration path to ULTRA-3 and beyond.
When the IMP5245/5246 are enabled, the differential sense (DIFF-
SENSE) pin supplies a voltage between 1.2V and 1.4V. The terminator
DIFFSENSE output is connected to the system DIFFSENSE line. If there
are no single ended or HVD devices attached to the system the LVD
output will be enabled. If the DIFFSENSE line is LOW, indicating a
single ended device, the IMP5245/5246 output will be in a high-
impedance state. If the DIFFSENSE line is HIGH, indicating a high
Key Features
N 2.5pF typical disabled output capacitance
N Fast response
N No external V_REF capacitors required
N 5µA supply current in disconnect mode
N 20mA supply current during normal operation
N Logic command disconnects all termination lines
N Diffsense line driver
N Current limit and thermal protection
N Compatible with the pending SPI-2 LVD
specification
N Pin compatible to the UCC5640
voltage differential device, the IMP5245/5246 output will
also be in a high-impedance state.
The IMP5245/5246 ICs have a TTL compatible disconnect
pin. The IMP5245 is active LOW and the IMP5246 is active
HIGH. During sleep mode, power supply current is
reduced to just 5µA. During sleep mode all outputs are in
a high-impedance state. Also during sleep mode, the
DIFFSENSE function is disabled and is placed in a high-
impedance state.
Block Diagram
1.3V
DIFFSENSE
OUT
DIFFB
DISC
DISC (IMP5246)
V_CM
V_OS/2
R–
(–)
1.25V
V_OS/2
R+
(+)
5245/46_01.eps
© 2002 IMP, Inc.
408-432-9100/www.impweb.com
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