AP1270 Datasheet, PDF (1/7 Pages) Advanced Power Electronics Corp. – 3A SINK/SOURCE BUS TERMINATION REGULATOR

Advanced Power
Electronics Corp.
AP1270
3A SINK/SOURCE BUS TERMINATION REGULATOR
FEATURES
Ideal for DDR-I, DDR-II and DDR-III V_TT Applications
Sink and Source 3A Continuous Current
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL_18,
HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in TO-252-5L & ESOP-8 Packages
V_IN and V_CNTL No Power Sequence Issue
RoHS Compliant and 100% Lead (Pb)-Free
APPLICATION
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
DESCRIPTIOON
The AP1270 is a simple, cost-effective and high-
speed linear regulator designed to generate termination
voltage in double data rate (DDR) memory system to
comply with the JEDEC SSTL_2 and SSTL_18 or other
specific interfaces such as HSTL, SCSI-2 and SCSI-3
etc. devices requirements. The regulator is capable of
actively sinking or sourcing up to 3A while regulating an
output voltage to within 40mV. The output termination
voltage cab be tightly regulated to track 1/2V _DDQ by two
external voltage divider resistors or the desired output
voltage can be pro-grammed by externally forcing the
REFEN pin voltage.
The AP1270 also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely low
initial offset voltage, excellent load regulation, current
limiting in bi-directions and on-chip thermal shut-down
protection.
The AP1270 are available in the TO-252-5L &
ESOP-8 (Exposed Pad) surface mount packages.
TYPICAL APPLICATION
VCNTL=3.3V
VIN=2.5V/1.8V/1.5V
2N7002
EN
R1
VIN
VCNTL
CIN
CCNTL
RTT
AP1270
REFEN
VOUT
CSS
R2
GND
COUT
R_DUMMY
R₁ = R₂ = 100KΩ, R_TT = 50Ω / 33Ω / 25Ω
C_OUT,min = 10uF (Ceramic) + 1000uF under the worst case testing condition
C_SS = 1µF, C_IN = 470µF(Low ESR), C_CNTL = 47µF
Data and specifications subject to change without notice
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