R11-0868 Datasheet, PDF (7/16 Pages) A-Data Technology – ADDV1333W8G9 DDR3L-1333(CL9) 240-Pin VLP R-DIMM 8GB(1024Mx72-bits)

ADDV1333W8G9
DDR3L-1333(CL9) 240-Pin VLP R-DIMM
8GB(1024Mx72-bits)
Pin Description：
PIN
CK0,
/CK0
NAME
System Clock
FUNCTION
Active on the positive and negative edge to sample all inputs.
CKE0~CKE1
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at
least on cycle prior new command. Disable input buffers for power down in standby
/S0~/S1
Chip Select
Disables or Enables device operation by masking or enabling all input except CK, CKE and
L(U)DQM
A0~A15
Address
Row / Column address are multiplexed on the same pins.
(Row Address: A0~A15 , Column Address: A0~A9 , Auto precharge: A10/AP)
BA0~BA2
DQ0~DQ63
CB0~CB7
DQS0~DQS8,
/DQS0~/DQS8
Banks Select
Data
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data and check bit inputs / outputs are multiplexed on the same pins.
Data Strobe
Bi-directional Data Strobe
TDQS9~TDQS17,
/TDQS9~/TDQS17
Termination Data Strobe Termination Data Strobe
/RAS
Row Address Strobe Latches row addresses on the positive edge of the CK with /RAS low
/CAS
Column Address Strobe Latches Column addresses on the positive edge of the CK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD / VSS
Power Supply/Ground Power and Ground for the input buffers and the core logic.
VREFDQ
Power Supply reference Power Supply for reference.DQ,DM.VDD/2
VREFCA
Power Supply reference Power Supply for reference. Command , address, & control.VDD/2
VDDQ
Power Supply
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity
SDA
Serial data I/O
EEPROM serial data I/O
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