ADS6608A4A Datasheet, PDF (1/8 Pages) A-Data Technology – Synchronous DRAM(2M X 8 Bit X 4 Banks)

A-Data
Synchronous DRAM
ADS6608A4A
2M x 8 Bit x 4 Banks
General Description
The ADS6608A4A are four-bank Synchronous
DRAMs organized as 2,097,152 words x 8 bits x 4
banks.
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
ADS6608A4A-75
Pin Assignment
Frequency
133Mhz
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
Interface
LVTTL
Package
400mil 54pin TSOPII
1
54
Vss
2
53
DQ7
3
52
VssQ
4
51
NC
5
50
DQ6
6
49
VDDQ
7
48
NC
8
47
DQ5
9
46
VSSQ
10
45
NC
11
44
DQ4
12
43
VDDQ
13
42
NC
14
41
VSS
15
40
NC/RFU
16
39
DQM
17
38
CK
18
37
CKE
19
36
NC
20
35
A11
21
34
A9
22
33
A8
23
32
A7
24
31
A6
25
30
A5
26
29
A4
27
28
VSS
54-pin plastic TSOP II 400 mil
Rev 1 April, 2001
1